1. Field of the Invention
This invention relates to the field of physical circuit design and, more particularly, to the placement of a design.
2. Description of the Related Art
Designs for Field Programmable Gate Arrays (FPGA's) have become increasingly complex and heterogeneous. Modern FPGA designs can include a variety of different components or resources including, but not limited to, registers, block Random Access Memory (RAM), multipliers, processors, and the like. This increasing complexity makes placement of components within a circuit design more cumbersome.
Components of circuit designs traditionally have been placed together through a series of discrete phases or tasks. Each task is performed sequentially and independently of the others to place a particular set of components of the circuit design. For example, inputs and outputs (I/O's) are placed, local clock nets are placed, and global clock nets are placed.
The local clock net placement task assigns or constrains a local clock source, local clock loads, as well as the data components to be latched by the local clock, to physical locations on the chip or particular regions or areas of the circuit design. While local clock nets may be placed in a separate operation from other component types, the local clock net placement task is performed no differently than other placement tasks. That is, although local clock nets can be placed, any analysis as to whether the placement of the circuit design complies with design constraints is not performed until the signals of the circuit design are routed.
During routing, the local clock sources are given higher priority than other component types in an effort to minimize clock skew and clock signal delays. Despite the priority afforded to local clock sources during routing, when design constraints cannot be met with the current placement, the circuit design must be placed again. This can increase circuit development time as well as costs as the circuit design may require placement to be performed several times in order to meet timing requirements as specified by predetermined design constraints.
In any case, determinations as to whether the current placement is feasible are not made until after placement has finished and the signal routing phase has begun. What is needed is a technique for placing local clock nets that seeks to attain a feasible placement for a circuit design during the placement process and evaluate that placement during the placement process prior to routing signals of the circuit design.